SystemC 3.0.0
Accellera SystemC proof-of-concept library
sc_signal_rv_ports.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 sc_signal_rv_ports.h -- The resolved vector signal ports.
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2001-05-21
25
26 CHANGE LOG IS AT THE END OF THE FILE
27 *****************************************************************************/
28
29#ifndef SC_SIGNAL_RV_PORTS_H
30#define SC_SIGNAL_RV_PORTS_H
31
32
33#include <cstdio>
34
39
40namespace sc_core {
41
42// ----------------------------------------------------------------------------
43// CLASS : sc_in_rv<W>
44//
45// The sc_signal_rv<W> input port class.
46// ----------------------------------------------------------------------------
47
48template <int W>
50 : public sc_in<sc_dt::sc_lv<W> >
51{
52public:
53
54 // typedefs
55
57
60
64
65public:
66
67 // constructors
68
70 : base_type()
71 {}
72
73 explicit sc_in_rv( const char* name_ )
74 : base_type( name_ )
75 {}
76
77 explicit sc_in_rv( const in_if_type& interface_ )
78 : base_type( interface_ )
79 {}
80
81 sc_in_rv( const char* name_, const in_if_type& interface_ )
82 : base_type( name_, interface_ )
83 {}
84
85 explicit sc_in_rv( in_port_type& parent_ )
86 : base_type( parent_ )
87 {}
88
89 sc_in_rv( const char* name_, in_port_type& parent_ )
90 : base_type( name_, parent_ )
91 {}
92
93 explicit sc_in_rv( inout_port_type& parent_ )
94 : base_type( parent_ )
95 {}
96
97 sc_in_rv( const char* name_, inout_port_type& parent_ )
98 : base_type( name_, parent_ )
99 {}
100
101 sc_in_rv( this_type& parent_ )
102 : base_type( parent_ )
103 {}
104
105 sc_in_rv( const char* name_, this_type& parent_ )
106 : base_type( name_, parent_ )
107 {}
108
109
110 // destructor (does nothing)
111
112 virtual ~sc_in_rv()
113 {}
114
115
116 // called when elaboration is done
117 /* WHEN DEFINING THIS METHOD IN A DERIVED CLASS, */
118 /* MAKE SURE THAT THIS METHOD IS CALLED AS WELL. */
119
120 virtual void end_of_elaboration();
121
122 virtual const char* kind() const
123 { return "sc_in_rv"; }
124
125private:
126
127 // disabled
128 sc_in_rv( const this_type& );
129 this_type& operator = ( const this_type& );
130};
131
132
133// IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
134
135
136// called when elaboration is done
137
138template <int W>
139void
141{
142 base_type::end_of_elaboration();
143 // check if bound channel is a resolved signal
144 if( dynamic_cast<sc_signal_rv<W>*>( this->get_interface() ) == 0 ) {
145 this->report_error( SC_ID_RESOLVED_PORT_NOT_BOUND_, 0 );
146 }
147}
148
149
150// ----------------------------------------------------------------------------
151// CLASS : sc_inout_rv<W>
152//
153// The sc_signal_rv<W> input/output port class.
154// ----------------------------------------------------------------------------
155
156template <int W>
158 : public sc_inout<sc_dt::sc_lv<W> >
159{
160public:
161
162 // typedefs
163
165
168
173
174public:
175
176 // constructors
177
179 : base_type()
180 {}
181
182 explicit sc_inout_rv( const char* name_ )
183 : base_type( name_ )
184 {}
185
186 explicit sc_inout_rv( inout_if_type& interface_ )
187 : base_type( interface_ )
188 {}
189
190 sc_inout_rv( const char* name_, inout_if_type& interface_ )
191 : base_type( name_, interface_ )
192 {}
193
194 explicit sc_inout_rv( inout_port_type& parent_ )
195 : base_type( parent_ )
196 {}
197
198 sc_inout_rv( const char* name_, inout_port_type& parent_ )
199 : base_type( name_, parent_ )
200 {}
201
203 : base_type( parent_ )
204 {}
205
206 sc_inout_rv( const char* name_, this_type& parent_ )
207 : base_type( name_, parent_ )
208 {}
209
210
211 // destructor (does nothing)
212
213 virtual ~sc_inout_rv()
214 {}
215
216
217 // write the new value
218
219 using base_type::operator=;
221 { base_type::operator=(port_); return *this; }
222
223
224 // called when elaboration is done
225 /* WHEN DEFINING THIS METHOD IN A DERIVED CLASS, */
226 /* MAKE SURE THAT THIS METHOD IS CALLED AS WELL. */
227
228 virtual void end_of_elaboration();
229
230 virtual const char* kind() const
231 { return "sc_inout_rv"; }
232
233private:
234
235 // disabled
236 sc_inout_rv( const this_type& );
237};
238
239
240// IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
241
242
243// called when elaboration is done
244
245template <int W>
246void
248{
249 base_type::end_of_elaboration();
250 // check if bound channel is a resolved signal
251 if( dynamic_cast<sc_signal_rv<W>*>( this->get_interface() ) == 0 ) {
252 this->report_error( SC_ID_RESOLVED_PORT_NOT_BOUND_, 0 );
253 }
254}
255
256
257// ----------------------------------------------------------------------------
258// CLASS : sc_out_rv<W>
259//
260// The sc_signal_rv<W> output port class.
261// ----------------------------------------------------------------------------
262
263// sc_out_rv can also read from its port, hence no difference with
264// sc_inout_rv. For debugging reasons, a class is provided instead
265// of a define.
266
267template <int W>
269 : public sc_inout_rv<W>
270{
271public:
272
273 // typedefs
274
277
279
284
285public:
286
287 // constructors
288
290 : base_type()
291 {}
292
293 explicit sc_out_rv( const char* name_ )
294 : base_type( name_ )
295 {}
296
297 explicit sc_out_rv( inout_if_type& interface_ )
298 : base_type( interface_ )
299 {}
300
301 sc_out_rv( const char* name_, inout_if_type& interface_ )
302 : base_type( name_, interface_ )
303 {}
304
305 explicit sc_out_rv( inout_port_type& parent_ )
306 : base_type( parent_ )
307 {}
308
309 sc_out_rv( const char* name_, inout_port_type& parent_ )
310 : base_type( name_, parent_ )
311 {}
312
314 : base_type( parent_ )
315 {}
316
317 sc_out_rv( const char* name_, this_type& parent_ )
318 : base_type( name_, parent_ )
319 {}
320
321
322 // destructor (does nothing)
323
324 virtual ~sc_out_rv()
325 {}
326
327
328 // write the new value
329
330 using base_type::operator=;
332 { base_type::operator=(port_); return *this; }
333
334 virtual const char* kind() const
335 { return "sc_out_rv"; }
336
337private:
338
339 // disabled
340 sc_out_rv( const this_type& );
341};
342
343
344// IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
345
346} // namespace sc_core
347
348//$Log: sc_signal_rv_ports.h,v $
349//Revision 1.3 2011/08/26 20:45:44 acg
350// Andy Goodrich: moved the modification log to the end of the file to
351// eliminate source line number skew when check-ins are done.
352//
353//Revision 1.2 2011/02/18 20:23:45 acg
354// Andy Goodrich: Copyright update.
355//
356//Revision 1.1.1.1 2006/12/15 20:20:04 acg
357//SystemC 2.3
358//
359//Revision 1.2 2006/01/03 23:18:27 acg
360//Changed copyright to include 2006.
361//
362//Revision 1.1.1.1 2005/12/19 23:16:43 acg
363//First check in of SystemC 2.1 into its own archive.
364//
365//Revision 1.11 2005/09/15 23:01:52 acg
366//Added std:: prefix to appropriate methods and types to get around
367//issues with the Edison Front End.
368//
369//Revision 1.10 2005/06/10 22:43:56 acg
370//Added CVS change log annotation.
371//
372
373#endif
374
375// Taf!
const char SC_ID_RESOLVED_PORT_NOT_BOUND_[]
this_type & operator=(const data_type &value_)
sc_in_rv(const char *name_, in_port_type &parent_)
sc_in_rv(const char *name_, const in_if_type &interface_)
base_type::inout_port_type inout_port_type
sc_in_rv(this_type &parent_)
base_type::in_port_type in_port_type
sc_in_rv(const in_if_type &interface_)
sc_in_rv(const char *name_, inout_port_type &parent_)
sc_in_rv< W > this_type
base_type::in_if_type in_if_type
sc_dt::sc_lv< W > data_type
sc_in_rv(const char *name_)
virtual const char * kind() const
sc_in_rv(inout_port_type &parent_)
sc_in_rv(const char *name_, this_type &parent_)
virtual void end_of_elaboration()
sc_in< data_type > base_type
sc_in_rv(in_port_type &parent_)
sc_inout< data_type > base_type
sc_inout_rv(const char *name_)
sc_inout_rv< W > this_type
virtual const char * kind() const
sc_inout_rv(this_type &parent_)
sc_inout_rv(const char *name_, inout_if_type &interface_)
base_type::in_if_type in_if_type
virtual void end_of_elaboration()
this_type & operator=(const this_type &port_)
base_type::in_port_type in_port_type
base_type::inout_port_type inout_port_type
sc_inout_rv(inout_if_type &interface_)
sc_inout_rv(const char *name_, this_type &parent_)
base_type::inout_if_type inout_if_type
sc_inout_rv(inout_port_type &parent_)
sc_inout_rv(const char *name_, inout_port_type &parent_)
sc_dt::sc_lv< W > data_type
base_type::inout_port_type inout_port_type
base_type::data_type data_type
sc_out_rv(const char *name_, inout_port_type &parent_)
sc_out_rv(const char *name_)
base_type::inout_if_type inout_if_type
this_type & operator=(const this_type &port_)
sc_out_rv(const char *name_, inout_if_type &interface_)
sc_out_rv(const char *name_, this_type &parent_)
sc_out_rv(inout_port_type &parent_)
sc_inout_rv< W > base_type
base_type::in_if_type in_if_type
sc_out_rv(this_type &parent_)
sc_out_rv(inout_if_type &interface_)
sc_out_rv< W > this_type
virtual const char * kind() const
base_type::in_port_type in_port_type